PDE and PTE

Both PDE and PTE are 32-bits in length.

The higher order 20 bits (12 to 31) contains the base address of the PTE or page. The address is expanded to 32 bits implicitly by adding trialing 12 zeros.

Avail field (bit 9 to 11) indicat if the entry is available for OS use. 

Global (G) flag (bit 8) is ignored in PDE. In PTE, it help to keep frequently accessed pages from flushing out of TLB

Bit 7 in PDE represents page size. When clear, 4KB page is used. In PTE, the bit represents the Page Attribute Table (PAT).

Bit 6 is clear in PDE. In PTE, it indicate if the page is dirty (written to)

Access (bit 5) indicates if the page has been accessed recently (both read or write)

PCD (bit 4) is the page cache disabled flag. When set, the page or page table will not be cached.

PWT (bit 3) is the page write through flag. When set, page write through is enabled for this page or page table 

U/S (bit 2) indicates if the page has user or supervisor privilege 

R/W (bit 1) specifies the protection for this page. Set means R/W and clear means R/O for the page the entry points to

P (bit 0) is the Present bit which indicates if the page or page table is loaded in memory currently (set)