Creating a separate lock for each resources incurred high overheads to maintain them. Creating too few locks will inhibit concurrency. A balanced approach is to group related programs that share resources and create separate lock for each group. In this case the groups of program can process without serializarion interrupted by other group of programs to achieve a balanced concurrency.
Locks are represented by a memory location. CPU attempt to obtain the lock by using compare and swap instruction to store its CPU id to the lock word location. CPU can repeatedly tried to obtain the lock by looping on the compare and swap instruction until it succeeds. This is called spin lock.
SRB is scheduled for execution via a SCHEDULE macro which linked the SRB to either the global or local chain in CVT.
Dispatcher will dispatch the global SRB before the local ones. When control is given to the SRB routine, it will first free the SRB storage as the dispatcher is not going to do so. SRB is executed with interupt enabled. But dispatcher will return control to SRB routine when the interrupt is handled. Dispatcher will not pre-empt the SRB unit of work until it gives up control voluntarily. This is to avoid saving and restoring state for a presumed short piece of work.
SRB can be suspended when t hits a page fault or it asking for a lock that is not available.in this case, SRB execution cannot continue. The page fault handler or lock manager would save the state of execution to a special SRB (SSRB”. Once the resources requested is available, the SSRB will be chained to the local SRB list with a special priority called non-quiesceable”
When an address space is quiesced, dispatcher will runs the SSRB to finish before the address space is stopped.
To execute a program in MVS, one can call the ATTACH macro which create a TCB. The ATTACH macro is expanded to a SVC call (42) which trigger interrupt handling. If the task was a performing very short procedure, the overhead of creating a task is too expensive.
MVS provide a SRB mechanism to allow a subsystem or address space to perform a procedure with less overhead than via creating a task. SRB is invoked via a SCHEDULE macro which does not expand to a SVC instruction. The macro will put the SRB on the appropriate queue and awaiting execution when the address space is picked by dispatcher as the next highest priority to run
In a multiprocessor systems that several CPU share the same memory, it is important to serialize access to specific memory cell to prevent different CPU overwrites the cell from each others.
For example, one CPU read the cell content into ALU register, add 1 and store it back to the cell. If the execution is interrupted and the value of the cell is changed by another CPU, the value stored will be overwritten by the first CoU when it resume its execution at a later time not realising the cell value has changed.
Compare and swap a a hardware interlocking mechanism to prevent this scenario. To use it, a CPU will read the value into the register (first parameter). He CS can instruction then compare the register value with the memory location. If the compare is equal, CS will store the register value (second parameter) to the memory location. If the compare is not equal, CS will store the value at the memory location to the first parameter register. In the latter case, the program need to handle the fact that the memory value has changed and retry the CS instruction until it is successful.
When the UPL device address is dialed and operator pressed the load button, the system reads in 24 bytes from the device.
The first 8 bytes is a PSW. The second bytes is a CCW which read in a channel program to fetch in the system start up code. The third 8 bytes s a TIC CCW which transfer control to the new channel program read in by the previous CCW.
Once the system start up code is read in, the system will load the PSW with the first 8 bytes to start the bootstrapping.
