When the processor initiates a transaction on the FSB, the logic external to the processor takes the least 2 significant bits of the address as always zero. In other word, the processor can only address memory locations at Dword boundary. The processor implement 4 output pins (BE0# to BE3$) instead to address individual byte in the Dword. (Each BE pin is used to select a separate memroy bank DIMM?) For example, for location zero of the Dwrod, the processor asserts BE0# pin and the target byte will be output over data path 0 (D[7:0]). For location three of the Dword, the processor asserts BE3# pin and the data will be output over data path 3 (D[31:24]).
To execute this instruction - mov eax,[0101], processor will need to access address locations at 0100 and 0104 (Dword boundary). Then it extracts the last 3 bytes from 0100 and the first byte from 1004 to form the final Dword to be loaded in eax. This degrades performance. Moreover, it could further trigger double cache misses or page misses. Therefore, Dword alignment of data is important. Starting from 486, all IA32 procssors will flag out this condition (Aligment Check Exception).
