Interrupt

Interrupt service routine (ISR) or interrupt handler is triggered to handle the event.  In real mode, the first 1K address 0x000 to 0x3FF contains the IVT (interrupt vector table).  In protected mode, the structure is called IDT (interrupt descriptor table).  Both IVT and IDT map interrupts to the ISRs.

In real mode, IVT stores the logical address of each ISR sequentially.  Each entry is 4 bytes - 2 for the segment selector and 2 for the effective address.  The IVT contains 256 entries.

Under MSDOS, the BIOS handle interrupt 0-31.  DOS system calls map to interrupts 32-63.  The remaining 64-255 interrupts are user defined.

There are 3 types of interrupts:
(1) hardware interrupts (external interrupts) are generated by external devices.  They are either maskable or non-maskable.  Maskable interrupts can be disabled by clearing the IF flag using the CLI instruction.  Non-maskable interrupt cannot be ignored and will always be handled by the processor.

(2) Software interrupts (internal interrupts) are implemented in programs using INT instruction.  INT takes an integer operand which represent the interrupt vector to invoke.  INT clears the TF (Trace Flag) and IF (no tracing and disable interrupt while executing), pushes FLAGS, CS, IP onto the stack (save the state and return address), jump to the ISR until IRET.

(3) Exceptions are generated when processor detects an error when execute an instruction.  There are 3 types of exception which differ in how the error is reported and how the instruction is restarted.  When a fault occurs, the processor reports the exception at the boundary preceding the offending instruction.  In other words, the state is reset to allow the instruction to restart.  Interrupt 0 (divided by zero) is an example of a fault.  When a trap occurs, no instruction restart is possible.  The processor report it at the boundary preceding the next instruction.  Example of traps are 3 (breakpoint) and 4 (overflow).  When an abort occurs, the program cannot be restarted.

In protected mode, the IDT stores an array of 64-bit gate descriptors.  These gate descriptor can be interrupt gate, trap gate or task gate.

Unlike IVT, IDT exists in any location in the linear address space.  The 32-bit base address of the IDT is stored in the 48-bit IDTR register (position 16 to 47).  The size of IDT (in bytes) stored in but 0 to 15.  IDTR can be manipulated by LIDT and SIDT instructions.  Reference beyond the IDT size limit will generate a general-protection exception.  As in real mode, the maximum number of IDT entries is 256.  Entry 0 to 31 is reserved by IA-32 processor for various interrupts and exceptions.

Gate descriptors allow programs to access code segments with different privilege levels.  Gate descriptors are system descriptor (with S-flag cleared).  The types of gate descriptor are encoded in the TYPE field.  Gates can be 16-bit or 32-bit.  This allows the systems to determine if the stack push is 16- or 32-bit variant.

Call Gate Descriptors live in GDT.  Instead of storing 32-bit base linear address line a code or data segment, it stores a 16-bit segment selector and 32-bit offset address.  The segment selector references a code segment in the GDT.  The offset address points to the entry point of the linear address of the procedure in the segment.  In effect, it is a descriptor in GDT points to another descriptor (via selector) in GDT points to a code segment (then applies the offset address).

To jump to a new segment using a call gate have 2 conditions:
(1) CPL of program and RPL of the selector for the call gate <= DPL of the call gate descriptor
(2) CPL of program >= DPL of the destination code segment

Interrupt gate and trap gate descriptors behave like call gate, except they reside in the Interrupt Descriptor Table (IDT).  The segement selector specified a code segment in GDT.  The effective address points to the entry point of the service routine in the segment.  So both descriptor ends up in GDT.  The only difference between interrupt gate and trap gate is that processor will clear the IF in EFLAGS when access bis interrupt gate.  For trap gate, IF value remains.

For security check, CPL of program invoking the handler must be less than or equal to the DPL of the gate.  This condition only holds when the handling routine is invoked by software (e.g INT).  The DPL of the segment selector points to the code segment must be less of equal to the CPL