DRAM and SRAM

DRAM are charge-based devices, where each bit is represented by a electrical charge stored in a very small capacitor. The charge can be leaked away in a short amount of time, so the system has to continuously refreshed to prevent the data from being lost. The act oreading also discharges te bit, requiring refresh. It is not possible to read the memory bit in DRAM while refresh takes place.

SRAM is based on gates and each bit stored in four to six connected transistors. SRAM retains the data as long as there is power, without the need to refresh.

Access time is the amount of time takes to read or write a memory location. Memory cycle time describe how often you can repeat reference to the same memory chip.

Fast page mode DRAM saves time by allowing a mode in which the entire address doesn't have to be re-clocked into the chip for each memory operation. Instead, there is an assumption that the memory will be accessed sequentially and only the low-order buts of the address are clocked in for successive reads or writes.

EDO RAM is a modification to output buffering on page mode RAM that allows it to operate roughly twice as fast for operation other than refresh.

Synchronous DRAM is sychnorized using an external clock that allows the cache and DRAM to coordinate their operations. Also SDRAM can pipeline the retrieval of multiple memory bits to improve overall throughput.

Cached DRAM contains a SRAM cache on the same chip as the DRAM. This improves performance to close to SRAM.