Perspective, or angles between the lines lends the illusion of depth. With perspective, 3D object can be depicted in 2D screen.
When one covers one eye and looks, the world still appears as in 3D because perspective alone is enough to create the 3D effect. Another obvious clue is nearby objects appear larger than the distant ones. This perspective effect is called foreshortening.
To enhance 3D effect in drawing on 2D, another technique is to remove hidden lines and surfaces from the object on screen. Applying different color to different side of object simulates the effects of light. Adding shadow further enhances the illusion.
Texture mapping takes an image, such as a photo and applies it on the surface of an object to give it a realistic looks. For example, applying wood texture onto a cube to make it looks like a box. The process of stretching and compressing texels (texture elements) is called filtering.
Fog adds haziness to objects in a scene depending on the distance where objects are.
Blending is the combination of colors or objects on the screen, similar to superimposing 2 images. By varying the amount of each object with the scene, one can make the effect of transparency. Blending can create the illusion of reflection.
Antialiasing blends the lines with the background color to eliminate the jagged edges.
Sunday, April 10, 2011
Saturday, April 2, 2011
CISC and RISC
If RISC is faster, why was CISC predominant in the past? Back then, computer had very little storage. An instruction that could roll up several steps of complex operation, such as a do-loop, into a single instruction was an advantage, because memory was precious. In addition, instruction fetch was piecemail and sequential. Reducing the number of instruction saved time.
As it turned out, assembly langauage progreammers used the complicated machine instructions but compilers generally did not. It was difficult enough for compiler to recognize when a complicated instruction could be used, but the real problem was code optimizations. Verbatim translation of source constructs isn't very efficient. An optimizing compiler works by simplifying and eliminating redundant computations, After optimization, opportunities to use the complicated instructions tended to disappear.
On the other hand, there were several pushes for the development of RISC.
(1) The number of transistors that could fit on a single chip was increasing.
(2) Techiques like pipelining was difficult to be implemented for variable length instruction common in CISC design.
(3) As compilers improved, the resulting code generated for RISC out-performed equivalent complicated multi-cycle instructions in CISC.
As it turned out, assembly langauage progreammers used the complicated machine instructions but compilers generally did not. It was difficult enough for compiler to recognize when a complicated instruction could be used, but the real problem was code optimizations. Verbatim translation of source constructs isn't very efficient. An optimizing compiler works by simplifying and eliminating redundant computations, After optimization, opportunities to use the complicated instructions tended to disappear.
On the other hand, there were several pushes for the development of RISC.
(1) The number of transistors that could fit on a single chip was increasing.
(2) Techiques like pipelining was difficult to be implemented for variable length instruction common in CISC design.
(3) As compilers improved, the resulting code generated for RISC out-performed equivalent complicated multi-cycle instructions in CISC.
DRAM and SRAM
DRAM are charge-based devices, where each bit is represented by a electrical charge stored in a very small capacitor. The charge can be leaked away in a short amount of time, so the system has to continuously refreshed to prevent the data from being lost. The act oreading also discharges te bit, requiring refresh. It is not possible to read the memory bit in DRAM while refresh takes place.
SRAM is based on gates and each bit stored in four to six connected transistors. SRAM retains the data as long as there is power, without the need to refresh.
Access time is the amount of time takes to read or write a memory location. Memory cycle time describe how often you can repeat reference to the same memory chip.
Fast page mode DRAM saves time by allowing a mode in which the entire address doesn't have to be re-clocked into the chip for each memory operation. Instead, there is an assumption that the memory will be accessed sequentially and only the low-order buts of the address are clocked in for successive reads or writes.
EDO RAM is a modification to output buffering on page mode RAM that allows it to operate roughly twice as fast for operation other than refresh.
Synchronous DRAM is sychnorized using an external clock that allows the cache and DRAM to coordinate their operations. Also SDRAM can pipeline the retrieval of multiple memory bits to improve overall throughput.
Cached DRAM contains a SRAM cache on the same chip as the DRAM. This improves performance to close to SRAM.
SRAM is based on gates and each bit stored in four to six connected transistors. SRAM retains the data as long as there is power, without the need to refresh.
Access time is the amount of time takes to read or write a memory location. Memory cycle time describe how often you can repeat reference to the same memory chip.
Fast page mode DRAM saves time by allowing a mode in which the entire address doesn't have to be re-clocked into the chip for each memory operation. Instead, there is an assumption that the memory will be accessed sequentially and only the low-order buts of the address are clocked in for successive reads or writes.
EDO RAM is a modification to output buffering on page mode RAM that allows it to operate roughly twice as fast for operation other than refresh.
Synchronous DRAM is sychnorized using an external clock that allows the cache and DRAM to coordinate their operations. Also SDRAM can pipeline the retrieval of multiple memory bits to improve overall throughput.
Cached DRAM contains a SRAM cache on the same chip as the DRAM. This improves performance to close to SRAM.
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