Demand Paging in 386

Segmentation complicates programming. Paging can be used to present a flat 32-bit (4GB) address space and yet provide protection among tasks. There is no way to switch off segmentation in the processor. However, if all segments defined in GDT was set to R/W, start at 00000000h and 4GB in legnth, segmentation is effectively eliminated.

Paging is enabled by setting PG bit in CR1 to 1. The paging unit intercepts all 32-bit linear memory addresses generated by the segment unit and perform a redirection mapping using a 2-level page table structure.

The top 10 bits of the linear address is used to index into the page directory to yield the base address of the Page table. The next 10 bits of the linear address is then used to index into the Page Table to yield the start address of the memory page. The last 12 bits is then used to access the location as offset.

If the Page Table was not in memory, a page fault is triggered. The linear address is latched into CR2 so that it could be accessed by the OS's page fault handler. When the target page is not in memory, similar action is performed.

TLB (Translation Lookaside Buffer) is used to short-circuit the look up. The segment unit sends the linear address to both TLB and Paging Unit. The top 20-bits of the linear address is compared against the cached entries in the TLB. If a match is found, it will disable the paging unit and send the corresponding 20-bits physical address mapping onto the FSB for retrieval.