Maskable interrupt can be generated by hardware or software by asserting the INTR line. They are maskable because programmer can disable the processor from recgonizing the INTR signal or disable the interrupt controller from accepting the interrupt request from selected device.
Non-Maskable interrupt (NMI) is generated by the chipset when serious hardware problem was detected in the system board. The processor's NMI input is asserted.
Software exception
Software exception refers to the problem when executing an instruction or its operands. The processor attempts to recovery gracefully by invoking a special exception handler.
A fault is an exception reported at the start of the instruction that caused the exception. The instruction can be restarted after the handler fixes the problem (e.g. page fault). A trap is an exception reported after the offending instruction has been executed. An abort does not always reliably supply the instruction that caused the problem. This makes it impossible for the exception handler to fix the problem and resume program execution.
Monday, December 7, 2009
Demand Paging in 386
Segmentation complicates programming. Paging can be used to present a flat 32-bit (4GB) address space and yet provide protection among tasks. There is no way to switch off segmentation in the processor. However, if all segments defined in GDT was set to R/W, start at 00000000h and 4GB in legnth, segmentation is effectively eliminated.
Paging is enabled by setting PG bit in CR1 to 1. The paging unit intercepts all 32-bit linear memory addresses generated by the segment unit and perform a redirection mapping using a 2-level page table structure.
The top 10 bits of the linear address is used to index into the page directory to yield the base address of the Page table. The next 10 bits of the linear address is then used to index into the Page Table to yield the start address of the memory page. The last 12 bits is then used to access the location as offset.
If the Page Table was not in memory, a page fault is triggered. The linear address is latched into CR2 so that it could be accessed by the OS's page fault handler. When the target page is not in memory, similar action is performed.
TLB (Translation Lookaside Buffer) is used to short-circuit the look up. The segment unit sends the linear address to both TLB and Paging Unit. The top 20-bits of the linear address is compared against the cached entries in the TLB. If a match is found, it will disable the paging unit and send the corresponding 20-bits physical address mapping onto the FSB for retrieval.
Paging is enabled by setting PG bit in CR1 to 1. The paging unit intercepts all 32-bit linear memory addresses generated by the segment unit and perform a redirection mapping using a 2-level page table structure.
The top 10 bits of the linear address is used to index into the page directory to yield the base address of the Page table. The next 10 bits of the linear address is then used to index into the Page Table to yield the start address of the memory page. The last 12 bits is then used to access the location as offset.
If the Page Table was not in memory, a page fault is triggered. The linear address is latched into CR2 so that it could be accessed by the OS's page fault handler. When the target page is not in memory, similar action is performed.
TLB (Translation Lookaside Buffer) is used to short-circuit the look up. The segment unit sends the linear address to both TLB and Paging Unit. The top 20-bits of the linear address is compared against the cached entries in the TLB. If a match is found, it will disable the paging unit and send the corresponding 20-bits physical address mapping onto the FSB for retrieval.
Segmentation in IA32 Real Mode
The start address of the segment must be within the first 1M memory space. The length of segment is fixed to 64KB (most significant 16 bits in the address). There is also no protection of segment among tasks.
The 64K memory above 1M line is called extended memory or HMA (High memory area). In real mode, one can access HMA by setting the segment register to xFFFF. For example,
mov ax,ffff
mov ds,ax
mov al,[0010]
The effective address - FFFF0+0010=10000.
This method is not effective for 8086/8088 which does not have A20 pin. Instead, the address will be wrapped around to 0000 (segment wrapping).
The 64K memory above 1M line is called extended memory or HMA (High memory area). In real mode, one can access HMA by setting the segment register to xFFFF. For example,
mov ax,ffff
mov ds,ax
mov al,[0010]
The effective address - FFFF0+0010=10000.
This method is not effective for 8086/8088 which does not have A20 pin. Instead, the address will be wrapped around to 0000 (segment wrapping).
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