FLIH copies the registers in LCCA (saved by the interrupt) to TCB register save area. It then try to acquire a local lock (to the address space it runs in) conditionally. If the lock is granted, it set a flag to indicate it got the local lock, enable interrupt for io and external. It then obtains the other lock required based on the SVC table entry and call the handler.
If the local lock cannot be granted, FLIh decrement the PSW instruction address by 2. PSW is saved in RB. So PSE is now pointing to the SVC instruction. FLIH then calls dispatcher to dispatch the next highest task in system. When the TCB becomes the highest task again, it becomes a resistance and retry the SVC call.
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