Prefixing

MVS use the first 4K page as save area for interrupt PSW. This is called PSA (prefix save area). Each interrupt has a slot to keep the old PSW of the current process and the new PSW used by the first level interrupt handler. In a multi CPU installation, we will need multiple 4K pages for this and each page is used for 1 CPU. Prefixing is used to do that. 

Each CPU has a PVR (prefix value register) which is 12 bit long. DAT translate virtual address referenced by the CPU into a real address the real address top 12 bit (assuming 24 bit addressing) is compare with the PVR value of the CPU. 

If the top 12 bit is zero (ie refer to the first 4K address), the 0s are replaced by PVR value and this form the absolute address. This is equivalent to transpose the fist 4K real dress to another block of real address. This is called forward prefixing. 

If the top 12 bits is not 0 and also does not match the PVR value, the real address remains unchanged and becomes the absolute address. 

If the top 12 bits match the PVR value, the prefixing hardware replace the top 12 bits with 0, effectively point it to the first real 4K memory block. This block of memory is used by the system ti store hardware I formation which can be inspected by all CPUs in the system. This is called reversed prefixing