Creating a separate lock for each resources incurred high overheads to maintain them. Creating too few locks will inhibit concurrency. A balanced approach is to group related programs that share resources and create separate lock for each group. In this case the groups of program can process without serializarion interrupted by other group of programs to achieve a balanced concurrency.
Locks are represented by a memory location. CPU attempt to obtain the lock by using compare and swap instruction to store its CPU id to the lock word location. CPU can repeatedly tried to obtain the lock by looping on the compare and swap instruction until it succeeds. This is called spin lock.
SRB is scheduled for execution via a SCHEDULE macro which linked the SRB to either the global or local chain in CVT.
Dispatcher will dispatch the global SRB before the local ones. When control is given to the SRB routine, it will first free the SRB storage as the dispatcher is not going to do so. SRB is executed with interupt enabled. But dispatcher will return control to SRB routine when the interrupt is handled. Dispatcher will not pre-empt the SRB unit of work until it gives up control voluntarily. This is to avoid saving and restoring state for a presumed short piece of work.
SRB can be suspended when it hits a page fault or it asking for a lock that is not available. In this case, SRB execution cannot continue. The page fault handler or lock manager would save the state of execution to a special SRB (SSRB) so the execution can continue to completion when the wait is over. Once the resources requested is available, the SSRB will be chained to the local SRB list with a special priority called non-quiesceable. When an address space is quiesced, dispatcher will let the SSRB to finish before the address space is stopped or otherwise work by SRB is half done and may cause data integrity. Thus the non-quiesceable property of SSRB.
To execute a program in MVS, one can call the ATTACH macro which create a TCB. The ATTACH macro is expanded to a SVC call (42) which trigger interrupt handling. If the task was a performing very short procedure, the overhead of creating a task is too expensive.
MVS provide a SRB mechanism to allow a subsystem or address space to perform a procedure with less overhead than via creating a task. SRB is invoked via a SCHEDULE macro which does not expand to a SVC instruction. The macro will put the SRB on the appropriate queue and awaiting execution when the address space is picked by dispatcher as the next highest priority to run
In a multiprocessor systems that several CPU share the same memory, it is important to serialize access to specific memory cell to prevent different CPU overwrites the cell from each others.
For example, one CPU read the cell content into ALU register, add 1 and store it back to the cell. If the execution is interrupted and the value of the cell is changed by another CPU, the value stored will be overwritten by the first CoU when it resume its execution at a later time not realising the cell value has changed.
Compare and swap a a hardware interlocking mechanism to prevent this scenario. To use it, a CPU will read the value into the register (first parameter). He CS can instruction then compare the register value with the memory location. If the compare is equal, CS will store the register value (second parameter) to the memory location. If the compare is not equal, CS will store the value at the memory location to the first parameter register. In the latter case, the program need to handle the fact that the memory value has changed and retry the CS instruction until it is successful.
When the UPL device address is dialed and operator pressed the load button, the system reads in 24 bytes from the device.
The first 8 bytes is a PSW. The second bytes is a CCW which read in a channel program to fetch in the system start up code. The third 8 bytes s a TIC CCW which transfer control to the new channel program read in by the previous CCW.
Once the system start up code is read in, the system will load the PSW with the first 8 bytes to start the bootstrapping.
Before IOS issue a SIO command, it firstly must set up the address of the channel program, a eries of channel command words in a special memory location called channel status word. If the channel responded positively to SIO, the channel start fetching and executing channel programs and frees the CPU to do other words.
Channel command word contains the command codes such as read or write, the data address n memory from or to which the data is the be transferred and several flags that nodify the execution of the command word.
Chain Data flag caused tue channel to continue execute the same command with the data address in the next word. This resulted in an effect of dispersed IO which read or write from few buffers.
Chain command flag caused the channel to execute the next command on the same device.
Skip flag caused the channel to read the data but not transmit to the memory. This is used to check the data just written (write check).
SLI suppresssed length indicator is to ask channel to not abend if the IO byte counts differs from the one specified in the command word. This is to handle variable length record.
TIC transfer in channel flag is the branch instruction in channel progra. CD and CC flag continue with TIC. If the next work is a TIC, the program will amend. If the next word is not CD or CD, it t indicated end of program.
In a job, each step runs a program. Control is passed to the program via an ATTACH macro. The macro has expanded to a SVC to ask supervisor to find and load the program and create a Request Block (RB) to indicate a level of control. Supervisor then pass control to it via BALR 14,15 wheee R14 contains the return address and R15 contains the load add re as of the program. ATTACH will also create a TCB
The program can issue LINK macro which ask supervisor to load another program and pass control to it. OS will create another RB for the called program to indicate another level of control. In other words, the called program will return control to the previous level when it issues a RETURN macro.
The XCTL macro is similar to link except it means called program return control not to the immediate caller but one higher level to the caller id the caller program. XCTL issue a SVC to replace the caller RB with the caller RB in the call chain
The LOAD macro loads a program and return the load address. However, no SVC is called this no RB is created. A caller can jump to the loaded program via a CALL macro and return to the caller via a RETURN macro.
RB are linked off from TCB. The TCB points to the latest called program. The foist called program for the step will be the last element in the project list and point back to the TCB.
MVS use the first 4K page as save area for interrupt PSW. This is called PSA (prefix save area). Each interrupt has a slot to keep the old PSW of the current process and the new PSW used by the first level interrupt handler. In a multi CPU installation, we will need multiple 4K pages for this and each page is used for 1 CPU. Prefixing is used to do that.
Each CPU has a PVR (prefix value register) which is 12 bit long. DAT translate virtual address referenced by the CPU into a real address the real address top 12 bit (assuming 24 bit addressing) is compare with the PVR value of the CPU.
If the top 12 bit is zero (ie refer to the first 4K address), the 0s are replaced by PVR value and this form the absolute address. This is equivalent to transpose the fist 4K real dress to another block of real address. This is called forward prefixing.
If the top 12 bits is not 0 and also does not match the PVR value, the real address remains unchanged and becomes the absolute address.
If the top 12 bits match the PVR value, the prefixing hardware replace the top 12 bits with 0, effectively point it to the first real 4K memory block. This block of memory is used by the system ti store hardware I formation which can be inspected by all CPUs in the system. This is called reversed prefixing
MVS reserved some amount of real storage set by a value in the IPL parameter. Region requested V=R will have its virtual storage same as the real storage. Two V=R regions will be mapped to different range in the real memory so they can share the reserved space. V=R region is not subjected to page fault and the storage is fixed in memory.
System Area occupies the low address range. System Area contains the nucleus load modules and nucleus extension. Nucleus load modules contains the dispatcher, interrupt handler and recovery support code. Nucleus also contains the CVT and page frame table. Nucleus extension contains fixed BLDL tables (device address of the program entries), fixed link pack area and other system-wise information. Nucleus starts at address 0 and the virtual addresses of System Area is same as real addresses.
Private Area is above the System Area. Private Area contains the user program in a region specified in the JOB card. To keep track of works and stroage in region, the Private Area also contains the LSQA and SWA. LSQA contains CB and tables related to the address space such as the segment table and page table. Subpool 253, 254 and 255 are in LSQA.
SWA is a work area of dispatcher. It contains subpool 236 and 237 which contains the job queue of the address space.
Private Area is pageable except the LSQA. When the address space is swapped in, LSQA will be fixed in real memory until the address space is swapped out.
Above Private Area is the Common Area. Common Area is common to all address spaces. Common Area contains the SQA, Pageable LPA and Common System Area. SQA contains tables and queues of the entire system and information related to all private address spaces. These information cannot be placed in LSQA which can be paged out with specific address space.
PLPA contains SVC routines, access method and other selected program. The routines are re-entrant. PLPA is pageable.
CSA is used for communication between address spaces.
System Area and Common Area are shared by and common to all address spaces. Their page tables are kept in SQA. Segment table and the private page tables are kept in LSQA
1. CPU Extended Control, EC-mode bit must be turned on in the PSW to enable DAT
2. Load the segment table address of the program in STOR
3. LPSW to load the program PSW with the translation bit (5) on
4. DAT verify the segment number is within the length of segment table (part of STOR). If out of range, program is terminated with 0C4.
5. DAT check the segment entry invalid bit. If it is 1. DAT returns segment translation error to OS
6. DAT checked the PTE and if GETMAIN bit is off, DAT returns program check error 0C4
7. If PTE invalid bit is off, the page is in main memory
8. If PTE invalid bit is on, a page fault is triggered and OS will bring the page in. During this time, the program lose control of CPU.
24 bit and 31 bit address will be padded with zeros on the left to 64 bit before DAT translate it or prefixing translate it
