TLB

Virtual memory translation is an expensive operation.  Translation Lookaside Buffer is used to improve performance by keeping the recently translated addresses without the need to go through the MMU (Memory Management Unit) and access to the page table stored in RAM.  TLB exploits both temporal and spatial locality.

When there is a context switch, the TLB must be flushed to avoid wrong translation.  All CPU provide a mean to flush the entire TLB or specific entries.  There is also mechanism to keep specific entry that do not changes across context switch as global entries.  Flushing TLB is a performance penalty.

From MMU's perspective, operating system access its own page table like any user process.  Therefore, no only TLB is flushed every context switch, it is also flushed at every entry/exit from kernel.  Moreover, kernel needs to access user memory (e.g. bring in arguments of a call or return result to user space).  For architecture such as x86/x86-64 that do not provide any hardware support to access context of another process, this situation results in TLB flushes at each kernel entry/exit and the need to access page tables each time a reference to another context is needed.  This has huge performance impact.

To reduce such performance impact, OS implement a combined user/kernel address space scheme (divide one address space of 4G into kernel portion and user portion).  Translated address entries in kernel area will be marked as accessible by by kernel code only.  These entries will not be flushed.

Some other architecture such as SPARC v9 provides sipport for accessing a context from inside another context and to associate TLB entires to specific context.  In such case, it is possible to separate kernel address space from user address space