Cache

Direct mapped cache - each cache line in memory maps directly to a fixed cache line position. If the cache is 4KB in size, every memory location in 4KB apart maps to the same cache line.

N-way associative cache - each cache line in memory maps to a set of N possible location in cache. The location chosen will be determined by some replacement policies (e.g. random or LRU etc).

Fully associative cache - each cache line in memory maps to any position in cache. This is rarely implemented because of its complexity

First level cache access time is 1 to 3 cycles.  Second level cache access time is 20 to 30 cycles.  Memory access takes more than 100 cycles.  The reason for having multiple level of cache because the larger the cach, the longer it takes to find out if an item is stored there.