Windows Program Set Up

WinMain is the main program in Windows.  Windows passed in 4 parameter when WinMain starts - Instance handle (type HINSTANCE), Previous instance handle (HINSTANCE), a pointer to the command line string (LPTSTR) and the options for the window to be created (INT).

the first step is to register the window calling RegisterClassEx with a WINCLASSEX structure. The structure contains parameter about the main window to be created like if it is to be redrawn when the window is resized horizontally or vertically, the program instance, pointer to the window's call back function, pointer to the icon and mouse etc.  The system call returns an integer - 0 if error and non-zero if ok. 

The WinMain calls CreateWindow function to create the first window.  It passes information about the window to be created like the title string, window style (e.g. overlapping), size and the application instance handle.  CreateWindow returns a handle to a HWD structure.

At this point, the window is still not visible, WinMain calls ShowWindow and UpdateWindow, passing the HWND handle to draws the window.

This complete the initialization.  WinMain then goes into a message loop to listen for messages to process. It calls GetMessage which will block the program until a message come in.  It then call TranslateMessage and DispatchMassage which passes the message to the call back function to process.

PCI

PCI was a parallel bus of 16 bit wide. PCI express change to use serial bus design. The protocol insert additional bits to achieve error for data inyegrity thus the data rate is less than the transfer capability.  The effective data rate improves from generation to generation by varying the amii pi unit of these overhead bits  

PCIe support full rate transfer bidirectionally. The standard support multi-lanes transfer from 1x to 32x. 

Winmain

This is the main routine in a windows program. It receives parameters from Windows include the instance handle that representing the current task, parameter passed to the program. If the program is already running, the usual treatment is for the program to terminate and this no new instance will run parallel to the existing instance. 

Serial data bus

Each bus consists of 2 lines to allow differential signalling that resist interference. 

Connections between the processor and the io chipset consists of several serial data buses called hsio (high speed io lanes). Each lanes may be dedicated to a specific device such as pcie, usb and sata etc. 

Parallel data bus

It uses multiple line for transfer. The limitation is a cap on the speed as satay propagation delay in each data line may differ. 

Another disadvantage is it can only operate in one direction at a time (half duplex). One needs another set of cable to achieve full duplex. 

GDDR

GDDR has wider data bus for throughput. SDDR on the other hand emphasizea latency. 

DDR

Double data rate DRAM means data transfer rate is doubled to the earliest RAM. The transfer happens at clock edges. 

Synchronous DRAM refers that the DRAM chip is synchronised zed with the memory controller through a shared clock. 

To increase transfer throughput, DDR4 device the memory into banks and grouping banks.  Transfer can be done simultaneously with multiple banks. 

Some systems implement multiple io controller that owns a set of bank to further increase throughput. Each controller is a channel. OS must be smart enough to layout the memory crosses the topology to maximize throughput. If all data is place in one bank, throughput is still serial. . 

DRAM

A bit is formed by a capacitor and a MOSFET gate. The capacitor restore the bit. 

To read, the control line of the gate is raised to drain the capacitor which represent a one of charge was stored. The current rent is latched in the chip output register for cpu.  To write, the control line is raised again to allow current flow to the capacitor but this time is to charge it. 

Capacitor leaks over time. So there is a need to recharge it and current recharge cycle is about 64 ms. The bit is read off and store back again in the refresh cycle. 

Core memory

Core memory use magnet to store data. To read off t data, the system attempts to set the core to 0. If the core already contain 0, there is no reaction. If the core contain 1, a pulse of current will be generated and detected. 

Core memory is persistent without electricity. It also resist to radiation (eg in space). 

Memory mapped io

Memory mapped io dedicated a part of system memory for io. Io is conducted using normal memory access instructions. 

Port mapped io uses special io instruction to perform the operation.  Some implementation will use an additional address line to differentiate the io instruction.

With expansion of addressable memory, common modern cpu uses memory mapped io interface la  

Programmed io means is to use program instruction to perform io. Os will constantly reading io status word to check if an io is done. This wasted cpu cycle.

Interrupt driven io uses interrupt signal and isr to perform the io. OS does not need to poll status word and thus more efficient. 

DMA is to further shorten the io processing time for transferring large amount of data. It freed cpu while data is being transferred between memory and device. Processor is to set up the parameters like address of transfer, length of data etc and a DMA controller will manage the transfer and interrupt the cpu when transfer is done