Each bus consists of 2 lines to allow differential signalling that resist interference.
Connections between the processor and the io chipset consists of several serial data buses called hsio (high speed io lanes). Each lanes may be dedicated to a specific device such as pcie, usb and sata etc.
It uses multiple line for transfer. The limitation is a cap on the speed as satay propagation delay in each data line may differ.
Double data rate DRAM means data transfer rate is doubled to the earliest RAM. The transfer happens at clock edges.
Synchronous DRAM refers that the DRAM chip is synchronised zed with the memory controller through a shared clock.
To increase transfer throughput, DDR4 device the memory into banks and grouping banks. Transfer can be done simultaneously with multiple banks.
Some systems implement multiple io controller that owns a set of bank to further increase throughput. Each controller is a channel. OS must be smart enough to layout the memory crosses the topology to maximize throughput. If all data is place in one bank, throughput is still serial. .
A bit is formed by a capacitor and a MOSFET gate. The capacitor restore the bit.
To read, the control line of the gate is raised to drain the capacitor which represent a one of charge was stored. The current rent is latched in the chip output register for cpu. To write, the control line is raised again to allow current flow to the capacitor but this time is to charge it.
Capacitor leaks over time. So there is a need to recharge it and current recharge cycle is about 64 ms. The bit is read off and store back again in the refresh cycle.
Core memory use magnet to store data. To read off t data, the system attempts to set the core to 0. If the core already contain 0, there is no reaction. If the core contain 1, a pulse of current will be generated and detected.
Core memory is persistent without electricity. It also resist to radiation (eg in space).
Memory mapped io dedicated a part of system memory for io. Io is conducted using normal memory access instructions.
Port mapped io uses special io instruction to perform the operation. Some implementation will use an additional address line to differentiate the io instruction.
With expansion of addressable memory, common modern cpu uses memory mapped io interface la
Programmed io means is to use program instruction to perform io. Os will constantly reading io status word to check if an io is done. This wasted cpu cycle.
Interrupt driven io uses interrupt signal and isr to perform the io. OS does not need to poll status word and thus more efficient.
DMA is to further shorten the io processing time for transferring large amount of data. It freed cpu while data is being transferred between memory and device. Processor is to set up the parameters like address of transfer, length of data etc and a DMA controller will manage the transfer and interrupt the cpu when transfer is done
