Core C states

 CC0 is active state with at least 1 thread running.  Clock gating may apply to part of the core unused. 

CC1 have most of the core clocks gated except some to keep coherence with other cores like snoop, cache and TLB is maintained. 

CC1e for enhanced to have frequency/voltage scaling applied to save more power. 

The exit latency for CC1 is about 1 u Sec  

CC3 used clock gating and use retention voltage  L1 and L2 are flushed  

CC6 employs power gating   Power to core is at 0  L1/2 cache and TLB are flushed  processor state stored outside and restore on wake  

CC3 and 6 uncut exit latency ip to 100 micro sec (u Sec)

CC8 to 10 are CC6 with additional power saving outside the core