DMERC

Domain message authentication reporting is used by a mail server to verify a received email is authorised to be sent from the domain and IP. It consists of sender policy framework (spf) and domain keys identified mail (skim) records. When a mail is received, the sender domain and ip is checked against the record and if not matched will be reported to the user. This could be used to detect phishing mail. This requires user to actively maintain the spf and dkim record for it to works. Also IP can be impersonated and so passing the check does not guarantee the mail is legitimate. 

Core C states

 CC0 is active state with at least 1 thread running.  Clock gating may apply to part of the core unused. 

CC1 have most of the core clocks gated except some to keep coherence with other cores like snoop, cache and TLB is maintained. 

CC1e for enhanced to have frequency/voltage scaling applied to save more power. 

The exit latency for CC1 is about 1 u Sec  

CC3 used clock gating and use retention voltage  L1 and L2 are flushed  

CC6 employs power gating   Power to core is at 0  L1/2 cache and TLB are flushed  processor state stored outside and restore on wake  

CC3 and 6 uncut exit latency ip to 100 micro sec (u Sec)

CC8 to 10 are CC6 with additional power saving outside the core 

Thread and core C states

 For CPU that support SMT, software can request the core to enter some thread C state. Each hardware thread can enter a different thread C state. If all thread requested thread C state, the CPU will enter into a corresponding core C state based in the shallowest thread C state requested. 

If a thread C state request does not induce a core C state, the power saving is minimal. 

When all cores in a package entered some deep C states, the package could entered into a package C state to further save power. 

Power saving states

C state refers to core state which power to the core parts are turned off to save power. There are different C state level with progressive longer exit latency. 

Package C state applies the techniques beyond the core to other components in the package like cache, integrate PCIe controller etc

P state refers to power state which frequency and voltage scaling is used to save power on the core or package level 

T state is to duty recycle core (shutdown the core). This is not so much to save power but to throttle to reduce thermal and power issues. 

S state refer to sleep state which drive the poster to near zero. This is usually employed in workstation but can also used for server. 

G state refers to global state which is similar to S state but apply to the whole platform. 

D state refers to device state which component like PCI card or drive is powered down to save power. 

Power saving strategies

 Power saving strategies may or may not save power if its usage is not engineered. Turning off a circuit trade off performance vs power consumption. However, other circuit waiting for the resumption of the part may wasted power during the waking up and overall power consumption reduction may be voided or even negated in some circumstances. 

Race to idle strategy is to operate the server at its peak performance at all time and jump into power saving mode when the work is cleared. This strategy usually not taken because of its impact to performance to long start up time from a deep state and also the power costumed in idle state to make it effective.   

Slow and steady strategy operate the server at level to process work continuously hourly without enter into power saving state. This is the most common strategy for server. 

Jog to idle strategy processes work at an optimal frequency and hip into power saving mode during work gap. The issue associate with this strategy is that the gap could be difficult to come by and few depending on the workload. 

Not off but reduce power

 Power consumption is proportional to frequency applied to a circuit part. If the work does not requires too performance, the frequency could be reduce to lower the power voltage consumed.  If the part is not needed for some time, just maintain the retention voltage level to that part to minimise power. 

Clock gating and power gating

Synchronous logic required clock signal to operate. Stopping clock signal to a part will reduce the active  power usage by that part. 

Power dating stop the power completely to a part. It saved both active power and stopped leakage too. 

To resume the operation for that part, clock gating takes less time then power gating (u sec vs n sec) because the latter need more time to restore its state in the circuit.