CML lock

Cross memory local lock refer to the LOCAL lock of an address space other than the home address space 

AR and cross memory

You cannot use AR to transfer control. To do this, you need to use either SRB or PC. PC routine can use AR to access data from the caller. It can also use MVCP (move to primary) or MVCS to access data in caller without using AR. 

Address translation mode

Home address space is where the work unit is dispatched. Primary address space indicates the segment tables used to fetch instruction is all address modes. Secondary address space indicates segment tables used to use to fetch data is the secondary ASC mode. 

ASC (access register address space control) mode determine how the processor resolve address in a program. 

In Primary ASC mode, processor does not use AR and fetch both instruction and data from the primary address space. 

In secondary ASC mode, processor does fetch instruction from the primary address space and data from the secondary address space. 

In AR ASC mode, processor uses AR to resolve address in address or data space. The program can move, compare and operate on data in other address space or data space. 

Cross memory communication in mvs

There is 2 ways to call service provided by another address space. 

Asynchronous cross memory communication is via SRB. For example, VTAM schedule a SRB to the address space waiting for the terminal data when it arrives  

Synchronous cross memory is via PC call.  Service provider is responsible to save the registers and status of the caller in the processor provided linkage stack, and restore them before returning (called stacking PC). Service provider set up the environment using macros and created a PC number for the caller to call. 

Storage SVC

Getmain and Freemain resolved into SVC 4, 5, 10 and 120. SVC 10 and 120 are used for both get and freemain. A flag in register differentiate between these 2 requests. After processing, control is given the Exit Prolog like other SVC. 

GETMAIN storage types

Request type ELEMENT asks for a single area of specific length. VARIABLE type asks for an area with size between 2 values. LIST type asks for one or more areas with specific size. 

MVS storage managers

VSM tracks storage allocation in virtual memory for each address space via subpools. It monitors and limits virtual storage request. 

RSM deals with the use or real memory. It handle paging with support from ASM. 

ASM manage the paging dataset and maintain accounting info for address space pages 

Local SRB dispatching

Dispatcher loops through the LSMQ and move the SRB to LSPL of each address space the SRB associated with. Each time an SRM is moved to the list, dispatcher invoke MSR and at the end, PSAANEW would contain the highest priority ASCB. 

Dispatcher compare PSAANEW and PSAAOLD to determine if a higher priority address space is now ready. If yes, it load the segment origin to CR1. Dispatcher will then look for work in the address space until all done. It the. Switch to the next priority highest address space.  

Global SRB dispatching

 Dispatcher follows the pointer in CVT to find the GSMQ (global service manager queue). GSMQ is like a staging queue. Dispatcher loops through the queue and issue SCHEDULE to the SRB which insert them into GSPL (global service priority queue). GSPL has 2 sub queues. One is non-quiescable SRB and one is normal system SRB. Dispatcher distribute the GSMQ to these 2 queues. 

Dispatcher then goes through GSPL to select one for dispatching. First it check if the system is no dispatches or and if it is, is the ASCB associated with this SRB is in the exemption list. ( the reason for the exemption is because some address spaces need to run to bring the system back from wait state). 

Dispatcher continue the following check to make sure the SRB is dispatchable before running it:

- is the SRB is dispatchable or not.

- if the address space associated with this SRB is dispatchable

- is all SRB STOP indicator is off

When the SRB passes the test, dispatcher update PSAAOLD with the ASCB address and set up the environment (load the segment origin to CR1, increase counter in ASCB, set up return address back to dispatcher in R14 etc)  dispatcher then issues LPSW to transfer control to the SRB  note tha PSAANWW is not updated for global STB processing 

Dispatcher Logic Overview

Dispatcher firstly checks if any exit processing is to be taken. Example of exits are cpu auto recovery, vary cpu or time of day clock updates. 

Next dispatcher checks if any global SRB was s ready to run. When this is done, dispatcher post SRB in the request queue to their respective address spaces. It is because SRB has same dispatching priority as the address space processing it. 

Next, dispatcher checks if any local supervisor works has been interrupt and now can resumed. Local supervisor now runs as enabled which could be interrupted. 

Next is to dispatch works (SRB and TCB) in address space. 

Lastly when no work in the system is available, dispatcher dispatch the WAIT ASCB (0) which place the system in wait state until the next interrupt triggers. 

Memory switching routine

MSR is called by supervisory functions such as ASCBCHAP, lock release, DEQ etc of which new work is made available.  MSR compares the priority of the new work va the existing active address space and if higher, update PSAANEW with the address of ASCB of the new work. 

In multiprocessor system, MSR compares the priority against the address spaces in all CPU and update one of them if the condition matches. It then generated a SIGP interrupt to the CPU and forced an entry into the dispatcher even if the CPU may be in Wait state with no outstanding dispatch able works. 

MVS Dispatcher switch

Dispatcher will look for some in 2 conditions. Firstly is ASCB address stored ib PSAANEW is different from PSAAOLD. It indicate  la higher priority work is available. Secondly is the current active address space has no more dispatcher work. 

I/O interrupt at MVS

IO interrupt could be generated from the device or from the channel program. For the latter, the program may encountered program check or unit check or busy exception stays of the devices. The interrupt handler located in the necleus will save the registers and call I/O supervisor to handle the request 

PcFLIH handling 2

 For interrupt code 0C1 to F, FLIH n the da to determine if control should be given to SPIE or RTM.

The following. Condition will pass control to RTM with call type =PROGMCK:

(1) PSW is set to have IO and external interrupt =disabled 

(2) process is in SRB mode 

(3) process holding locks 

(4) process is in supervisor state 

If the process does not have an active SPIR, RTM is called. Else control is give to SPIE. FLIH will set up a SRB with info from the SPIE control blocks. It then make the TCB to be no dispatches or, decrease the ready TCB count of the add re as space by 1, schedule the SRB and give control to dispatcher. 

PCFLIH handling 1

When a program check happened, the first level interrupt handler would get control. It saves the PSW, registers and interrupt length code  in LCCA. 

If it is a translation exception, it set a recursive indicator. 

If this is not the first time translation exception occurrence, special processing started. For the first recursion, load R1 with the master segment table and abend the address space. For the second recursion terminate the entire system and placed in wait state

Antivirus types

Two types - one works in based on signature and one based on heuristic. A signature is a segment of code that represented a virus. The signature is compare against a database so this tupe of antivirus works on known virus that infected enough target to be picked up. Heuristic antivirus looks at network pattern for anomalies. It must be trained to recognize what normal looks like. It is typically deploy in network choke points like proxies and firewalls. 

Bootkit

 Bukit modifies boot sector and is difficult to detect as it is launched before the antivirus software loaded. It can be detected via a scan initiated from a secure device like usb. Some os supports secure boot of which it will examine the boot record before start booting. 

DMERC

Domain message authentication reporting is used by a mail server to verify a received email is authorised to be sent from the domain and IP. It consists of sender policy framework (spf) and domain keys identified mail (skim) records. When a mail is received, the sender domain and ip is checked against the record and if not matched will be reported to the user. This could be used to detect phishing mail. This requires user to actively maintain the spf and dkim record for it to works. Also IP can be impersonated and so passing the check does not guarantee the mail is legitimate. 

Core C states

 CC0 is active state with at least 1 thread running.  Clock gating may apply to part of the core unused. 

CC1 have most of the core clocks gated except some to keep coherence with other cores like snoop, cache and TLB is maintained. 

CC1e for enhanced to have frequency/voltage scaling applied to save more power. 

The exit latency for CC1 is about 1 u Sec  

CC3 used clock gating and use retention voltage  L1 and L2 are flushed  

CC6 employs power gating   Power to core is at 0  L1/2 cache and TLB are flushed  processor state stored outside and restore on wake  

CC3 and 6 uncut exit latency ip to 100 micro sec (u Sec)

CC8 to 10 are CC6 with additional power saving outside the core 

Thread and core C states

For CPU that support SMT, software can request the core to enter some thread C state. Each hardware thread can enter a different thread C state. If all thread requested thread C state, the CPU will enter into a corresponding core C state based in the shallowest thread C state requested. 

If a thread C state request does not induce a core C state, the power saving is minimal. 

When all cores in a package entered some deep C states, the package could entered into a package C state to further save power. 

Power saving states

C state refers to core state which power to the core parts are turned off to save power. There are different C state level with progressive longer exit latency. 

Package C state applies the techniques beyond the core to other components in the package like cache, integrate PCIe controller etc

P state refers to power state which frequency and voltage scaling is used to save power on the core or package level 

T state is to duty recycle core (shutdown the core). This is not so much to save power but to throttle to reduce thermal and power issues. 

S state refer to sleep state which drive the poster to near zero. This is usually employed in workstation but can also used for server. 

G state refers to global state which is similar to S state but apply to the whole platform. 

D state refers to device state which component like PCI card or drive is powered down to save power. 

Power saving strategies

 Power saving strategies may or may not save power if its usage is not engineered. Turning off a circuit trade off performance vs power consumption. However, other circuit waiting for the resumption of the part may wasted power during the waking up and overall power consumption reduction may be voided or even negated in some circumstances. 

Race to idle strategy is to operate the server at its peak performance at all time and jump into power saving mode when the work is cleared. This strategy usually not taken because of its impact to performance to long start up time from a deep state and also the power costumed in idle state to make it effective.   

Slow and steady strategy operate the server at level to process work continuously hourly without enter into power saving state. This is the most common strategy for server. 

Jog to idle strategy processes work at an optimal frequency and hip into power saving mode during work gap. The issue associate with this strategy is that the gap could be difficult to come by and few depending on the workload. 

Not off but reduce power

 Power consumption is proportional to frequency applied to a circuit part. If the work does not requires too performance, the frequency could be reduce to lower the power voltage consumed.  If the part is not needed for some time, just maintain the retention voltage level to that part to minimise power. 

Clock gating and power gating

Synchronous logic required clock signal to operate. Stopping clock signal to a part will reduce the active  power usage by that part. 

Power dating stop the power completely to a part. It saved both active power and stopped leakage too. 

To resume the operation for that part, clock gating takes less time then power gating (u sec vs n sec) because the latter need more time to restore its state in the circuit.