Storage SVC

Getmain and Freemain resolved into SVC 4, 5, 10 and 120. SVC 10 and 120 are used for both get and freemain. A flag in register differentiate between these 2 requests. After processing, control is given the Exit Prolog like other SVC. 

GETMAIN storage types

Request type ELEMENT asks for a single area of specific length. VARIABLE type asks for an area with size between 2 values. LIST type asks for one or more areas with specific size. 

MVS storage managers

VSM tracks storage allocation in virtual memory for each address space via subpools. It monitors and limits virtual storage request. 

RSM deals with the use or real memory. It handle paging with support from ASM. 

ASM manage the paging dataset and maintain accounting info for address space pages 

Local SRB dispatching

Dispatcher loops through the LSMQ and move the SRB to LSPL of each address space the SRB associated with. Each time an SRM is moved to the list, dispatcher invoke MSR and at the end, PSAANEW would contain the highest priority ASCB. 

Dispatcher compare PSAANEW and PSAAOLD to determine if a higher priority address space is now ready. If yes, it load the segment origin to CR1. Dispatcher will then look for work in the address space until all done. It the. Switch to the next priority highest address space.  

Global SRB dispatching

 Dispatcher follows the pointer in CVT to find the GSMQ (global service manager queue). GSMQ is like a staging queue. Dispatcher loops through the queue and issue SCHEDULE to the SRB which insert them into GSPL (global service priority queue). GSPL has 2 sub queues. One is non-quiescable SRB and one is normal system SRB. Dispatcher distribute the GSMQ to these 2 queues. 

Dispatcher then goes through GSPL to select one for dispatching. First it check if the system is no dispatches or and if it is, is the ASCB associated with this SRB is in the exemption list. ( the reason for the exemption is because some address spaces need to run to bring the system back from wait state). 

Dispatcher continue the following check to make sure the SRB is dispatchable before running it:

- is the SRB is dispatchable or not.

- if the address space associated with this SRB is dispatchable

- is all SRB STOP indicator is off

When the SRB passes the test, dispatcher update PSAAOLD with the ASCB address and set up the environment (load the segment origin to CR1, increase counter in ASCB, set up return address back to dispatcher in R14 etc)  dispatcher then issues LPSW to transfer control to the SRB  note tha PSAANWW is not updated for global STB processing 

Dispatcher Logic Overview

Dispatcher firstly checks if any exit processing is to be taken. Example of exits are cpu auto recovery, vary cpu or time of day clock updates. 

Next dispatcher checks if any global SRB was s ready to run. When this is done, dispatcher post SRB in the request queue to their respective address spaces. It is because SRB has same dispatching priority as the address space processing it. 

Next, dispatcher checks if any local supervisor works has been interrupt and now can resumed. Local supervisor now runs as enabled which could be interrupted. 

Next is to dispatch works (SRB and TCB) in address space. 

Lastly when no work in the system is available, dispatcher dispatch the WAIT ASCB (0) which place the system in wait state until the next interrupt triggers. 

Memory switching routine

MSR is called by supervisory functions such as ASCBCHAP, lock release, DEQ etc of which new work is made available.  MSR compares the priority of the new work va the existing active address space and if higher, update PSAANEW with the address of ASCB of the new work. 

In multiprocessor system, MSR compares the priority against the address spaces in all CPU and update one of them if the condition matches. It then generated a SIGP interrupt to the CPU and forced an entry into the dispatcher even if the CPU may be in Wait state with no outstanding dispatch able works.